The invention relates to methods for fabricating thin film transistors, and more particularly, to methods for fabricating gate structures of thin film transistors.
Bottom-gate type thin film transistors (TFTs) are widely used in thin film transistor liquid crystal displays (TFT-LCDs). FIG. 1A is a cross section of a conventional bottom-gate type TFT structure 100. The TFT structure 100 typically comprises a glass substrate 110, a metal gate 120, a gate insulating layer 130, a channel layer 140, an ohmic contact layer 150, a source 160 and a drain 170.
As the size of TFT-LCD panels increases, metals having low resistance are required. For example, gate lines-employ low resistance metals such as Cu and Cu alloy in order to improve operation of the TFT-LCD. Cu, however, has unstable properties such as poor adhesion to the glass substrate, which can cause a film peeling problem. Cu also has a tendency to diffuse into a silicon film and must be mixed with other metals such as Cr or Mg to increase the resistance thereof. Moreover, Cu is vulnerable to deformation. Specifically, in a plasma process of depositing a film, characteristic degradation such as roughness and resistance of Cu are increased due to reaction between Cu and the plasma during plasma enhanced chemical vapor deposition (PECVD).
U.S. Pat. No. 6,165,917 to Batey et al., the entirety of which is hereby incorporated by reference, discloses a method for passivating Cu layer. The method uses an ammonia-free silicon nitride layer as a cap layer covering a Cu gate.
U.S. Publication No. 2002/0042167 to Chae, the entirety of which is hereby incorporated by reference, discloses a method for forming a TFT. A metal layer such as Ta, Cr, Ti, or W is deposited on a substrate. A Cu gate is defined on the metal layer. Thermal oxidation is then performed to diffuse the material of the metal layer along the surface of the Cu gate, which is consequently surrounded by a metallic oxide.
FIG. 1B is a cross section of a conventional bottom-gate type TFT structure 100a. A metal gate 120 comprising a doped copper alloy or a solid solution copper alloy is formed on a glass substrate 110. Dopant or solute in the metal gate 120 diffuses to the surface of the metal gate 120 by heat treatment. An oxide layer 125 is formed after oxidation covering the metal gate 120. Resistivity Rs of the metal gate 120 comprising a doped copper alloy or a solid solution copper alloy is, however, very high and typically in a range of 4–8 μΩ·cm. As such, high resistivity cannot meet requirements for TFT devices.